Many timing circuits are known, such as those in which an initial voltage is permitted to decay to a lower set point voltage, with a comparator detecting when the set point voltage has been reached. Such timing circuits have dependencies upon system power supplies so that variations in a supply will affect the detected time interval; or a loss of a power supply voltage may render the timing circuit inoperative.
Some such timing circuits suffer timing inaccuracies due to temperature variations of the circuit components or differences in device characteristics from circuit to circuit.
It is the general aim of the invention to provide a timing circuit which overcomes, or greatly reduces the effect of, the foregoing disadvantages.